목록HLS (3)
yc0325lee
#ifndef DUT_H #define DUT_H #include "defines.h" SC_MODULE(dut) { sc_in_clk i_clk; sc_in i_resetn; sc_in i_valid; // input sc_out o_busy; sc_in i_coef[Y_SIZE][X_SIZE]; sc_in i_data[NDIM][NCHAN][Y_SIZE][X_SIZE]; sc_out o_valid; // output sc_in i_busy; sc_out o_data[NDIM][NCHAN]; u4_t count; // pipeline state variable SC_CTOR(dut) // constructor : count ( 8 ) { BEGIN; SC_CTHREAD(thread0, i_clk.pos..
module half_adder ( input wire a, input wire b, input wire cout, input wire sum ); assign sum = a ^ b; assign cout = a & b; endmodule module full_adder ( input wire a, input wire b, input wire cin, output wire cout, output wire sum ); wire g, p; // generate and propagate wire cp; // propagated-carry half_adder ha1 ( .a( a ), .b ( b ), .cout ( g ), .sum ( p ) ); half_adder ha2 ( .a( cin ), .b ( p..
// ---------------------------------------------------------------------------- // File : Divide_6_3_6_3.v // Author : yc0325lee // Created : 2022-04-26 23:20:53 by lee2103 // Modified : 2022-04-26 23:20:53 by lee2103 // Description : // Six bit by three-bit divider // At each stage we use an adder to both subtract and compare // The adders start 1-bit wide and grow to six bits wide // We check ..